Implementation of Self-Testing Carry Select Adder by using Two Pair Two Rail Checker Technique

Authors:SADANALA VENKATA MANI PRADEEP, K. RAJASEKHAR

0342-0345

An Improved Image Searching Method K-means Clustering

Authors:TALLAPRAGADA TEJASYA, SUDAHANI JYOTHI

0346-0351

Implementation of Hard Systematic Error-Correcting Codes using Verilog HDL

Authors:AMRUTAVAKKULA SRINIVAS, KASSEY RAJASEKHAR

0352-0356

Hardware Programming As an Alternative for Embedded System

Authors:T. HARNATH, K. LAL KISHORE

0357-0362

Study of CNTFET Performance over MOSFET using Digital Logic Circuits

Authors:ARSHI RIZVI, PALLAVEE JAISWAL

0363-0375

Comparative Analysis of low power 1-Bit Full Adder using XNOR Logic by Gate Diffusion Input (GDI) Technique with Header and Footer Sleep Transistors

Authors:SWAPNIL JAIN, SANDEEP KUMAR TOSHNIWAL

0376-0378

Implementation of Aging Aware Multiplier Based on Vedic Multiplication Algorithm

Authors:SURAVARAPU PARVATISWAR RAO

0379-0383

Detecting and Correcting Multiple Bit Upsets in Static Random Access Memories

Authors:A. GEETHANJALI, B. SUDHARANI

0384-0389

Implementation of Asynchronous FIFO and Interface It with UART

Authors:PREETI KUMARI, AKHIL SEHRAWAT, NEETIKA YADAV

0390-0394

Design & Implementation of I2C Master Controller Interfaced with RAM Using VHDL

Authors:BOYA NARESH, P. VIJAY LAKSHMI, T. MAHESHWAR, DIWAKAR TIWARY

0395-0398